The present invention relates to an integrated circuit that employs a combination of multiple non volatile memory cell structures. More particularly the present invention relates to a highly integrated circuit and a fabrication method for an one time programmable (OTP) memory integrated device in an embedded EEPROM array. Merely by way of example, the invention has been applied to an one time programmable erasable programmable read only memory (OTP EPROM) device in an embedded EEPROM array. But it would be recognize that the invention has a much broader applicability.
Integrated circuits have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Conventional integrated circuits provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of integrated circuits.
Increasing circuit density has not only improved the complexity and performance of integrated circuits but has also provided lower cost parts to the consumer. An integrated circuit or chip fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of integrated circuits on it. Therefore, by making the individual devices of an integrated circuit smaller and integrating more functions on a single chip, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller and integrating device function on a single chip is very challenging, as each process used in integrated device fabrication has a limit. That is to say, a given process typically only works down to a certain feature size and for certain device structure, and then either the process or the device layout needs to be changed.
As an example in digital systems, various types of memory devices have been proposed. Such memory devices include, among others, read only memory, commonly called ROM devices. The read only memory (ROM) device such as a mask ROM can be used in code storage on portions of the array of memory units. As merely an example, conventional mask ROM often includes a program photo mask set be used to input the codes in manufacturing process. Although such mask ROMs have been successful, conventional mask ROMs have certain limitations. That is, such conventional mask ROMs often suffer from a long coding lead time and inflexibility. The result is higher manufacturing cost.
From the above, it is seen that an improved and cost effective method for fabricating semiconductor devices including memory devices is desired.